1. Field of the Invention
This invention relates to methods and apparatus for read-out of MEMS capacitive transducers, especially MEMS microphones, and in particular to amplifier arrangements, such as low-noise amplifiers, with an improved input range.
2. Description of the Related Art
Micro-electromechanical-system (MEMS) transducers, such as MEMS microphones, are finding application in a range of devices. The MEMS transducer is typically connected to an amplifier to amplify the signal from the transducer. The amplifier is typically a type of low noise amplifier (LNA) which is connected close to the transducer to reduce losses from e.g. parasitic shunt capacitances before amplification.
FIG. 1a illustrates an example of a conventional pre-amplifier circuit for a MEMS capacitive transducer, in this example a MEMS microphone. A first plate of the capacitive transducer 101 is biased by a suitable bias voltage VBIAS, say 12V, and the second plate is connected to a reference voltage, typically ground, via a high impedance element RBM 102. The high impedance element 102 may have an impedance of the order of 25 GOhms or so and may, for example, be implemented by one or more polysilicon diodes. In use an acoustic stimulus incident on the transducer will deflect one of the plates of the transducer, thus changing the spacing of the plates and resulting in a change in capacitance. A measurement signal, Vin, is tapped between the second plate of transducer 101 and high-impedance element 102.
The input signal Vin from the transducer is received by an amplifier circuit comprising first and second transistors, 103a and 103b, in this example both being P-channel MOS transistors. The input signal Vin drives the gate of the first transistor, PMOS 103a, whilst the gate of the second transistor, PMOS 103b, is connected to ground. The sources of the first and second transistors 103a and 103b are effectively driven by current sources 104a and 104b respectively, and coupled via a resistance Rs 105 to provide a signal dependent current. The drains of the transistors 103a and 103b are each connected to the reference voltage by load resistors 106a and 106b such that the voltages at nodes DA and DB provide a differential voltage signal Vm1 representing the input signal. This differential voltage signal may be converted to a single ended signal Vout by amplifier 107 which may also apply some gain AV.
In use the PMOS 103a is typically operated in saturation, i.e. with a relatively high magnitude drain-source voltage Vds. As will be appreciated the saturation region for a PMOS occurs (assuming Vgs<VTP) when Vds≦Vgs−VTP, where VTP is the (negative) threshold voltage. Thus saturation occurs when Vdg≦−VTP. In other words the PMOS 103a will drop out of saturation if the drain voltage is more positive than the gate voltage by the magnitude of |VTP|. If the spacing of the plates of the capacitive transducer is changed by an incident stimulus such that the input signal Vin goes more negative than the drain voltage of PMOS 103a by an amount greater than |VTP| the PMOS 103a will drop out of saturation. This effect is exacerbated by the fact that as Vin goes more negative the voltage at node DA goes more positive as illustrated in FIG. 1b. 
FIG. 1b illustrates how the voltages at nodes DA and DB vary with where the gate voltage of PMOS 103a is equal to Vin. It will be seen that if Vin is equal to ground then the voltage at node DA will have a certain positive value, equal in magnitude to the quiescent gate-source voltage Vgs0 of transistor MPA 103a required to support the quiescent drain current. In this example the current source 104a and load resistance 106a associated with PMOS 103a are matched to equivalent elements 104b, 106b of identical PMOS transistor 103b so at Vin=0 by symmetry the voltage at node DA matches the voltage at node DB. As Vin goes negative however more current flows through transistor 103a resulting in the voltage at node DA increasing until a point VinX is reached where the gate-drain voltage of transistor 103a equals the threshold. At this point the transistor will drop out of saturation into the linear or triode region of operation. The PMOS 103a will then struggle to pass sufficient current and the amplifier signal will become non-linear and eventually clip to some value.
The amplifier may only begin to clip for relatively large input signals, for instance an input sound level of 94 dBSPL may lead to a voltage swing of about 7 mV rms which may be within the range of saturation for the circuit shown in FIG. 1a. For at least some applications this may be sufficient and it may not matter that larger signal levels clip. However there are increasing demands to be able to handle higher signal levels. One way to address this problem and extend the negative input range is stabilise the voltage at node DA to a nominal bias voltage as illustrated in FIG. 2a. FIG. 2a shows a similar circuit to that illustrated in FIG. 1a where similar components are designated by the same reference numerals. In the circuit shown in FIG. 2a however the voltage at node DA is stabilised to a nominal bias voltage VBD applied to one input of differential amplifier 201a. The other input terminal of this differential amplifier is connected to node DA and the amplifier steers more or less current through the PMOS 103a and into the load resistor RLA 106a to stabilise the voltage across the resistor to equal VBD. This means that the current through PMOS 103a is stabilised to equal VBD/RLA and no longer changes with signal which can help to linearise this input stage. The source voltage for PMOS 103a, i.e. the voltage of node SA, follows Vin closely with a constant Vgs shift. Likewise differential amplifier 201b stabilises the voltage at node DB and thus the source voltage at node SB for PMOS 103b is forced to be a constant voltage (Vgs) above its gate voltage at ground. Thus a current equal to (V(SA)−V(SB))/RS=Vin/RS flows through resistor 105. This current modulation also flows through resistors 202a and 202b to provide an amplified differential voltage signal Vm1 across their lower terminals.
As illustrated in FIG. 2b, the PMOS 103a will now go out of saturation at the value VinY at which Vin is lower than the fixed voltage VDA by |VTP| rather than the smaller voltage VinX of FIG. 1b. Thus the negative input range of the amplifier circuit of FIG. 2a can be increased over that of the amplifier of FIG. 1a when biased similarly. For example with a typical bias voltage of around 200 mV, and a typical threshold voltage VTP of −600 mV, this means the input signal Vin, may go as low as −400 mV before the onset of clipping. An input range of this order would typically allow an input signal of the order of about 123 dBSPL before clipping. In some applications however there is a desire to allow even larger input signal levels without clipping. For instance to cope with a 129 dBSPL input signal would the amplifier circuit to be able to operate correctly with an input signal having a negative peak magnitude of the order of about 800 mV.